--- powerpc64/README | 73 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 powerpc64/README
diff --git a/powerpc64/README b/powerpc64/README new file mode 100644 index 00000000..19351be8 --- /dev/null +++ b/powerpc64/README @@ -0,0 +1,73 @@ +General-Purpose Register Conventions + +Register Status Use + +GPR0 volatile In function prologs. +GPR1 dedicated Stack pointer. +GPR2 dedicated Table of Contents (TOC) pointer. +GPR3 volatile First word of a function's argument list; + first word of a scalar function return. +GPR4 volatile Second word of a function's argument list; + second word of a scalar function return. +GPR5 volatile Third word of a function's argument list. +GPR6 volatile Fourth word of a function's argument list. +GPR7 volatile Fifth word of a function's argument list. +GPR8 volatile Sixth word of a function's argument list. +GPR9 volatile Seventh word of a function's argument list. +GPR10 volatile Eighth word of a function's argument list. +GPR11 volatile In calls by pointer and as an environment pointer + for languages that require it (for example, PASCAL). +GPR12 volatile For special exception handling required by certain + languages and in glink code. +GPR13 reserved Reserved under 64-bit environment; + not restored across system calls. +GPR14:GPR31 nonvolatile These registers must be preserved across + a function call. + +Vector Register Conventions + +Register Status + +VR0:V19 Volatile +VR20:VR31 Nonvolatile (extended ABI mode) their values are preserved + across function calls + +Addressing memory + +There are many ways to reference data, in the sake of writing +position-independent code the current implementation uses GOT-indirect +addressing (Accessing data through the global offset table): +1. Define data in .data section +2. Load the address of data into register from the global offset table + e.g. ld 7, my_var@got(2) +3. Use the address to load the value of data into register + e.g. ld 3, 0(7) +Refer to [2] for more information about referencing data + +VSX instructions "lxvd2x/stxvd2x" are used to load and store data to +memory instead of VR instructions "lvx/stvx" as it produces a fewer +instructions "lvx/stvx" can be used to load/store data into storage +operands but additional instructions are needed to access unaligned +storage operands, refer to "6.4.1 Accessing Unaligned Storage Operands" +in [3] to see an example of accessing unaligned storage operands. +"lxvd2x/stxvd2x" can be used to load/store data into unaligned storage +operands but permuting is needed for loading and storing data in +little-endian mode VSX registers are defined with "X" suffix +TODO: use architecture 3.0 instructions "lxv/stxv" instead for POWER9 + and newer + +Function Prologue + +Big-endian systems only support ELFv1 ABI which requires the following +steps in the function prologue: +1. Write the "official procedure descriptor" in ".opd","aw" section +2. Write procedure description for .my_func in my_func label +3. Switch back to ".text" section for program code +4. Label the beginning of the code .my_func +Refer to [1] for more information +Little-endian systems are compatible with ELFv2 ABI, an example of +function prologue for ELFv2 ABI can be seen in [2] + +[1] http://www.ibm.com/developerworks/linux/library/l-powasm1.html +[2] https://openpowerfoundation.org/?resource_lib=64-bit-elf-v2-abi-specificatio... +[3] https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b
Maamoun TK maamoun.tk@googlemail.com writes:
powerpc64/README | 73 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 powerpc64/README
Merged to the power-asm-wip branch (there were still some improper line breaks on the url-lines at the end; I had to edit a little before git am was happy with it). And I did the P8 -> p8 rename. If the ci tests work out fine, I'll merge to the master branch, and we can continue from there.
Regards, /Niels
On Sun, Aug 2, 2020 at 2:12 PM Niels Möller nisse@lysator.liu.se wrote:
Maamoun TK maamoun.tk@googlemail.com writes:
powerpc64/README | 73 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 powerpc64/README
Merged to the power-asm-wip branch (there were still some improper line breaks on the url-lines at the end; I had to edit a little before git am was happy with it). And I did the P8 -> p8 rename. If the ci tests work out fine, I'll merge to the master branch, and we can continue from there.
I'm not sure what you plan on doing with POWER9, but the POWER8 AES sources will be fine for POWER9.
POWER9 adds the DARN random number generator. DARN is like RDRAND or RDSEED. You can ask for a conditioned or unconditioned word. The rng is not available on POWER8.
See the POWER ISA 3.0 specification, p. 78.
Jeff
Thanks for the info, I'll take a look.
Regards, Mamone
On Sun, Aug 2, 2020 at 9:27 PM Jeffrey Walton noloader@gmail.com wrote:
On Sun, Aug 2, 2020 at 2:12 PM Niels Möller nisse@lysator.liu.se wrote:
Maamoun TK maamoun.tk@googlemail.com writes:
powerpc64/README | 73 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 powerpc64/README
Merged to the power-asm-wip branch (there were still some improper line breaks on the url-lines at the end; I had to edit a little before git am was happy with it). And I did the P8 -> p8 rename. If the ci tests work out fine, I'll merge to the master branch, and we can continue from there.
I'm not sure what you plan on doing with POWER9, but the POWER8 AES sources will be fine for POWER9.
POWER9 adds the DARN random number generator. DARN is like RDRAND or RDSEED. You can ask for a conditioned or unconditioned word. The rng is not available on POWER8.
See the POWER ISA 3.0 specification, p. 78.
Jeff _______________________________________________ nettle-bugs mailing list nettle-bugs@lists.lysator.liu.se http://lists.lysator.liu.se/mailman/listinfo/nettle-bugs
nisse@lysator.liu.se (Niels Möller) writes:
Merged to the power-asm-wip branch (there were still some improper line breaks on the url-lines at the end; I had to edit a little before git am was happy with it). And I did the P8 -> p8 rename. If the ci tests work out fine, I'll merge to the master branch, and we can continue from there.
Merged to master now. So this branch now includes fat setup and the AES implementation. I'm also testing the ABI fix (I did it slightly differently, applying only to powerpc64) on the master-updates branch.
Please try it out, in particular, check that it still gives the expected performance improvement.
Regards, /Niels
Great. I can confirm the testsuite is passed and the performance of AES is as expected for both fat and explicit crypto configurations.
On Sat, Aug 29, 2020 at 4:14 PM Niels Möller nisse@lysator.liu.se wrote:
nisse@lysator.liu.se (Niels Möller) writes:
Merged to the power-asm-wip branch (there were still some improper line breaks on the url-lines at the end; I had to edit a little before git am was happy with it). And I did the P8 -> p8 rename. If the ci tests work out fine, I'll merge to the master branch, and we can continue from there.
Merged to master now. So this branch now includes fat setup and the AES implementation. I'm also testing the ABI fix (I did it slightly differently, applying only to powerpc64) on the master-updates branch.
Please try it out, in particular, check that it still gives the expected performance improvement.
Regards, /Niels
-- Niels Möller. PGP-encrypted email is preferred. Keyid 368C6677. Internet email is subject to wholesale government surveillance.
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