--- powerpc64/README | 86 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 powerpc64/README
diff --git a/powerpc64/README b/powerpc64/README new file mode 100644 index 00000000..6d6f3fbb --- /dev/null +++ b/powerpc64/README @@ -0,0 +1,86 @@ +General-Purpose Register Conventions + +Register Status Use + +GPR0 volatile In function prologs. +GPR1 dedicated Stack pointer. +GPR2 dedicated Table of Contents (TOC) pointer. +GPR3 volatile First word of a function's argument list; + first word of a scalar function return. +GPR4 volatile Second word of a function's argument list; + second word of a scalar function return. +GPR5 volatile Third word of a function's argument list. +GPR6 volatile Fourth word of a function's argument list. +GPR7 volatile Fifth word of a function's argument list. +GPR8 volatile Sixth word of a function's argument list. +GPR9 volatile Seventh word of a function's argument list. +GPR10 volatile Eighth word of a function's argument list. +GPR11 volatile In calls by pointer and as an environment pointer for languages + that require it (for example, PASCAL). +GPR12 volatile For special exception handling required by certain languages and in + glink code. +GPR13 reserved Reserved under 64-bit environment; not restored across system calls. +GPR14:GPR31 nonvolatile These registers must be preserved across a function call. + +Vector Register Conventions + +Register Status + +VR0 Volatile +VR1 Volatile +VR2 Volatile +VR3 Volatile +VR4 Volatile +VR5 Volatile +VR6 Volatile +VR7 Volatile +VR8 Volatile +VR9 Volatile +VR10 Volatile +VR11 Volatile +VR12 Volatile +VR13 Volatile +VR14 Volatile +VR15 Volatile +VR16 Volatile +VR17 Volatile +VR18 Volatile +VR19 Volatile +VR20:31 Nonvolatile (extended ABI mode) their values are preserved across function calls + +Addressing memory + +There are many ways to reference data, in the sake of writing position-independent code +the current implementations uses GOT-indirect addressing (Accessing data through the global +offset table): +1. Define data in .data section +2. Load the address of data into register from the global offset table e.g. ld 7, my_var@got(2) +3. Use the address to load the value of data into register e.g. ld 3, 0(7) +Refer to [2] for more information + +VSX instructions "lxvd2x/stxvd2x" are used to load and store data to memory +instead of VR instructions "lvx/stvx" as it produces a fewer instructions +"lvx/stvx" can be used to load/store data into storage operands +but additional instructions are needed to access unaligned storage operands, refer +to "6.4.1 Accessing Unaligned Storage Operands" in [3] +to see an example of accessing unaligned storage operands. "lxvd2x/stxvd2x" can +be used to load/store data into unaligned storage operands but permuting is needed +for loading and storing data in little-endian mode +VSX registers are defined with "X" suffix +TODO: use architecture 3.0 instructions "lxv/stxv" instead for POWER9 and newer + +Function Prologue + +Big-endian systems only support ELFv1 ABI which requires the following steps in the +function prologue: +1. Write the "official procedure descriptor" in ".opd","aw" section +2. Write procedure description for .my_func in my_func label +3. Switch back to ".text" section for program code +4. Label the beginning of the code .my_func +Refer to [1] for more information +Little-endian systems are compatible with ELFv2 ABI, an example of function prologue +for ELFv2 ABI can be seen in [2] + +[1] http://www.ibm.com/developerworks/linux/library/l-powasm1.html +[2] https://openpowerfoundation.org/?resource_lib=64-bit-elf-v2-abi-specificatio... +[3] https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b
Maamoun TK maamoun.tk@googlemail.com writes:
powerpc64/README | 86
Hi, this patch still has lien break problems, e.g.,
+GPR11 volatile In calls by pointer and as an environment pointer for languages
- that require it (for example, PASCAL).
this line break makes it invalid patch syntax. Unclear to me where and why that happens; the mail was sent using
Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64
so MTAs on the way won't care about line length. I could fix it manually and apply, but maybe it's better to reformat the README file to keep line length limited to 72 or so characters.
You could also have a look at the x86_64/README and arm/README files, to use the same table style, e.g.,
Registers May be Argument clobbered number
r0 Y 1 r1 Y 2 r2 Y 3 r3 Y 4 r4 N
(Not essential, but consistency would make it a bit easier for readers).
Regards, /Niels
Hi,
I reformatted the README as you suggested and re-wrote line breaks to avoid the invalid ones.
Regards, Mamone
On Fri, Jul 31, 2020 at 9:40 PM Niels Möller nisse@lysator.liu.se wrote:
Maamoun TK maamoun.tk@googlemail.com writes:
powerpc64/README | 86
Hi, this patch still has lien break problems, e.g.,
+GPR11 volatile In calls by pointer and as an environment pointer
for
languages
- that require it (for example, PASCAL).
this line break makes it invalid patch syntax. Unclear to me where and why that happens; the mail was sent using
Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64
so MTAs on the way won't care about line length. I could fix it manually and apply, but maybe it's better to reformat the README file to keep line length limited to 72 or so characters.
You could also have a look at the x86_64/README and arm/README files, to use the same table style, e.g.,
Registers May be Argument clobbered number
r0 Y 1 r1 Y 2 r2 Y 3 r3 Y 4 r4 N
(Not essential, but consistency would make it a bit easier for readers).
Regards, /Niels
-- Niels Möller. PGP-encrypted email is preferred. Keyid 368C6677. Internet email is subject to wholesale government surveillance.
nettle-bugs@lists.lysator.liu.se